Уменьшение числа LUT-элементов в схеме совмещенного автомата

Abstract

Предложен метод синтеза совмещенного микропрограммного автомата в базисе FPGA, позволяющий получить схему с минимальным числом элементов LUT и встроенных блоков памяти EMB. Минимизация достигается путем замены части множества логических условий и соответствующего кодирования состояний автомата. Приведен пример применения метода.

Запропоновано метод синтезу суміщеного мікропрограмного автомата в базисі FPGA, що дозволяє отримати схему з мініма льним числом елементів LUT і вбудованих блоків пам'яті EMB. Мінімізація досягається шляхом заміни частини множини логічних умов та відповідного кодування станів автомата. Наведено приклад застосування методу.

A method for synthesis of combined finite state machine (CFSM) with FPGA is proposed. An analysis of CFSM’s peculiarities is given. The main feature of CFSM is an existence of two types of the output signals. Mealy outputs depend on the both inputs and states. Moore outputs depend only on the states. The known methods of CFSM design and conditions for their application and the method of the logical conditions replacement is thoroughly analyzed. It allows using embedded memory locks (EMB) for implementing some part of CFSM circuit. It is shown that the situations are possible when not all address inputs of an EMB are used. The suggested method is based on using these free address inputs. It is proposed to connect a part of logical conditions with unused address inputs of EMB blocks. It allows diminishing for the number of look-up table (LUT) elements in the circuit of logical conditions replacement in comparison with known methods of CFSM design. It is proposed to replace some part of the logical conditions set by additional variables. A design method based on such partial replacement is proposed. The method allows obtaining a CFSM circuit with the minimum number of table elements LUTs and memory blocks EMBs. Some additional optimization are possible for the replacement block of the logical conditions due to a special state assignment. The main idea of the special state assignment is reduced the assignment neighbor codes for states with transitions depending on the same logical conditions. It allows diminishing the number of the literals in functions implemented of the block of the logical conditions replacement. An example of the studied method application is shown. The proposed method allows obtaining a circuit required minimum chip space and consuming minimum power in comparison with the known design methods. The conducted researches are based on some library of standard GSAs. The investigations show that for the majority of standard GSAs the proposed method produces the circuits with a single EMB.