Рассмотрена задача формирования энергоемких тестов для комбинационных КМОП-схем по результатам моделирования их энергопотребления на различных видах тестовых последовательностей. Описаны соответствующие эксперименты. Для схем со многими входами целесообразно формировать тестовые пары псевдослучайных векторов с возможно большим расстоянием по Хэммингу.
Розглянуто задачу формування енергомістких тестів для комбінаційних КМОП-схем за результатами моделювання їх енергоспоживання на різних видах тестових послідовностей. Описано відповідні експерименти. Для схем з багатьма входами доцільно формувати тестові пари псевдовипадкових векторів з можливо великою відстанню за Хеммінгом.
One of the problem of decreasing the energy consumption of the logic CMOS circuits is the obtaining estimates for the energyintensive mode of a circuit. The approximate evaluations of the power consumption can be obtained by simulation of the structural descriptions in VHDL language in logical simulation systems. More accurate estimates for energy consumption can be received by using analog simulation systems. In both kinds of modeling for each pair testing sets applied to the input of the circuit, the result of modeling is the some value of power consumption presenting both the dynamic and static consumption, which occurs when transistor of logic CMOS elements of circuit are switched. The determination of the finite sequence of testing vectors, which provides the mode of the increased power consumption of the combinational CMOS circuit, can be implemented in three ways. The first method is to carry out logical simulation on a sufficiently large set of randomly generated testing vectors and then to select the some sets, on which the power consumption of circuit will be increased, from the original “big” test sequence. The second method is to form the required “energy-intensive” test sequence by taking into account the certain properties of test vectors without performing the initial modeling and irrespective of the circuit. The third method is based on the formation of a test sequence, which takes into account the structure of the logic circuit, requires an individual approach to each scheme and can only be used in very demanding applications. The problem of the energy-intensive tests formation for combinational CMOS circuits according to the results of their power consumption modeling on various types of test sequences in the first method is considered: on the randomly generated sets of the testing vectors; on the sets of truth tables; on the set of the ordered pairs of different testing vectors. The experiments shows that the complete set of ordered test vectors pairs allows to get the most energy-intensive tests, but this approach is applicable to the combinational circuits of small (no more than ten) number of input variables. The selection of energy-intensive test vectors was carried out by a program implementing a “greedy” algorithm. In the second method, the tests which consist of mutually inverse pseudorandom vectors pairs, are generated. The experimental results show that for the considered combinational CMOS circuits, the form of the initial tests influences the received energyintensive tests. In addition, it is proved that the use of the original pairs of the test vectors, characterized by a large Hamming distance, allows the obtaining high power consumption without an initial modeling and selection of the best test input pairs, as is done in first method.
